Features - Storage Innovations:

TOSHIBA and SanDisk ANNOUNCE NEW NAND CELL ARCHITECTURE

Toshiba Corporation and SanDisk Corporation have announced development of a high density NAND flash memory cell structure that allows fabrication of 4-Gigabit (Gb) NAND flash memory using the 90-nanometer (nm) design rules. The new memory cell has a physical cell area of only 0.041 micron squared, and supports scaling to future generations of smaller feature design rules. Toshiba and SanDisk have tested the new cell structure and demonstrated its performance and reliability. The two companies plan to employ the new NAND cell technology starting in the first half of 2004 with 2-Gigabit and 4-Gigabit NAND flash memory chips that will be manufactured by their FlashVision Japan Joint Venture production facility located at Toshiba's Yokkaichi Operations in Japan. Details of the high density NAND flash memory cell structure were presented at the VLSI Symposium in Kyoto, Japan, on June 11. Toshiba and SanDisk are recognized technology innovators and market leaders in NAND flash memories -- the highly versatile, non-volatile memory that continues to be designed into a diverse range of products, including digital still and video cameras, mobile phones and PDAs. Toshiba, a principal inventor of NAND flash memory, has consistently led the way in promoting advances in chip capacity, while SanDisk is a leader in flash data storage card products and a pioneer in high density flash MLC memory technology. In the new NAND memory cell structure, the floating gate is completely self-aligned to the active area. This design characteristic supports scaling of the structure for fabrication beyond the 90nm design rule and is expected to provide a distinct advantage over the current NAND memory cell structure, where further scaling below 110 nanometers becomes difficult. The new memory cell structure is designed to support both 2-Gigabit single-level cells (SLC) with an area per bit of 0.041 micron squared as well as 4-Gigabit multi-level cells (MLC), which effectively will have an area per bit of only 0.0205 micron square. The MLC structure allows each memory cell to carry 2 bits of information, instead of 1 bit, and minimizes interference. The larger capacity and low bit cost of MLC will allow Toshiba and SanDisk to reinforce their market leadership and advance their continuing collaboration in new technologies to meet increasing market demands for flash memory.