Features - Storage Innovations:

AGILENT INTRODUCES FIBRE CHANNEL CONTROLLER IC W/ EDC

Agilent Technologies Inc introduced the industry's first 2 Gb per second dual-channel Fibre Channel controller to include error detection code (EDC) for early detection of data corruption in storage subsystems. EDC ensures end-to-end data integrity from the host server to the target storage devices, providing companies with increased reliability and safeguarding of valuable corporate data.

"The ever-increasing speeds in storage require more rigorous measures to preserve data integrity," said Erik Ottem, marketing director of Agilent's Storage Networking Division. "Being first to market with EDC in silicon is another significant milestone for Agilent, and well positions the new Agilent Tachyon DX2+ chip with storage OEMs."

As data rates continue to evolve from 2 Gb per second to 4 Gb per second and 10 Gb per second, the need to detect and correct corrupted data becomes increasingly vital. Current techniques are based on proprietary schemes and lack the system-level interoperability necessary to provide universal SCSI error detection and correction. The Agilent HPFC-5600 Tachyon DX2+ Fibre Channel controller IC uses EDC to flag the data error and inform the memory subsystem's software driver. The driver can then take corrective measures to recover the I/O.

This fifth-generation Agilent Tachyon controller offers industry-leading performance for storage subsystems, SCSI to Fibre Channel bridges, host bus adapters and mid-to-high-end storage applications that use multi-processor systems. The dual-channel 2 Gb per second single-chip HPFC-5600 advances the existing Tachyon DX2 dual-channel architecture by combining a complete hardware-based solution that uses an EDC protection algorithm for interfacing between Fibre Channel mass storage devices and the main memory of the subsystem.

The Agilent HPFC-5600's EDC algorithm maintains the SCSI command structure and architecture model, and enables EDC to stay with the data for its entire life within the storage array. It allows a protection domain to be initiated, propagated and terminated by using a standard mechanism to guard the data, enhancing end-to-end data integrity.

The Agilent HPFC-5600 supports dual-channel, full duplex Fibre Channel port operation, which saves valuable board space for system manufacturers. It features 1 Gb per second and 2 Gb per second operation, and provides backward compatibility to previous-generation Tachyon controllers. The HPFC-5600 interfaces to the industry-standard 33 and 66 MHz PCI and 66/100/133 MHz PCI-X (enhanced PCI) bus architecture with 32 and 64-bit support. Agilent's proven state machine architecture scales proportionately with system CPU resources to avoid performance bottlenecks associated with on-chip processors. This architecture allows simultaneous, parallel processing of inbound data, outbound data, and hardware control and commands to maximize bandwidth and minimize latency and I/O overhead.