Features:

OSC EXAMINES GROWING FPGA MARKET WITH OCTOBER SYMPOSIUM
by Tim Curns, Editor

Field programmable gate arrays (FPGAs) have been around for a number of years, but attention is heating up now because of their potential to substantially accelerate some important HPC codes, and because a few vendors now offer products with FPGA capability. To catch up on FPGAs, HPCwire's Tim Curns interviewed Kevin Wohlever, project director of the Ohio Supercomputer Center's new facility in Springfield, Ohio. On October 4-5, 2004, OSC will host a pioneering symposium on FPGAs in collaboration with industry vendors.

HPCwire: What kinds of things are keeping you up at night while organizing this conference?

Wohlever: I was worried about attendance, because of the short time-line for the event, and the fact that this is a relatively new area of HPC for OSC, but the response has been tremendous. We were hoping for 20 participants and already have 43 registered, even without getting the word out widely. We hit a hot button in the HPC community. I don't know if there has just been a critical mass of people who think they can design a chip specific to their needs, or if it is the allure of the next technological frontier. People may be tired of depending on the hardware, compiler and library vendors dictating what can and cannot be done. This is another level of flexibility that may help solve specific needs of a particular user or group, that has started to become more widely available.

HPCwire: Do you have room for more people? How can people register?

KW: Sure, we welcome anyone interested in FPGAs to attend without charge. To register, go to http://www.osc.edu/springfield/xd1/index.shtml.

KW: The potential for directed applications to exploit them for substantially faster performance. Initial testing on a few applications has proven the potential. The next step is to apply FPGAs across more applications. Areas that OSC will look to applying the applications will be in making some high level languages more efficient, bioinformatic codes, gene sequencing, text matching, and signal image processing. We will also look at using the chips to help offload the main processor, doing such things as networking, MPI or OpenMP or even visualization on the FPGA -- things that you may want to do once in a while, but don't want to buy dedicated boardsets to do because of costs or bus real estate.

HPCwire: What might hinder FPGA adoption?

KW: Clearly, a major issue has been the programming environment. The compilers and the software stack aren't there yet. At OSC, we like the approach of creating open-source libraries around communities-of-interest. Then you can deploy the FPGA from the mainstream programming environment with just a library call. There's already a random number generator library like this for the Cray XD1 that's providing significant speed-ups. This is an important application for some users. We want to encourage other libraries to be created and shared. That's another thing we'll talk about on October 4 and 5.

HPCwire: When did OSC start looking at FPGAs?

KW: About three and a half years ago. FGPA investigation was built into a proposal that didn't get funded. We decided to pursue it on our own, initially with TimeLogic. When we heard about the speed ups that some codes such as BLAST were getting on the TimeLogic deCypher cards, we were intrigued. At OSC we are always on the lookout for new technology that will help meet the research needs of our users. The technology seems very cost effective. We wanted to understand and evaluate the issues with FPGA or reconfigurable computing.

In the future, all computing could be done on reconfigurable (FPGA) chips. Where the best software and libraries to program a chip will be more important than a dedicated chip design. Of course there are still many issues such as chip cost, programming speed, and execution speed that must be overcome.

HPCwire: How have FPGAs been used to date?

KW: Generally, to speed up the development of ASICs and other components. If you make a mistake, you reprogram the FPGA instead of sending the ASIC back to the foundry for a three-month re-spin. I am not qualified to discuss this area in any depth. I do know that I have been hearing about FPGA usage more and more in the design of new systems. They offer a way to easily prototype some functions, such as memory access or I/O, and make changes later in the design. It makes for easier upgrades, problem resolution or even providing a way to try different techniques.

HPCwire: What's the current status of FPGA technology?

KW: It can be used effectively on very specific applications with a limited programming environment. People are just starting to integrate FPGAs into general HPC environments, but this isn't proven out yet. But FPGAs have become a resource more people want to use, which is why we're hosting this symposium.

HPCwire: Aren't FPGAs a lot slower than microprocessors?

KW: For some applications they're slower, and for others they're a lot faster. For example, if you try to emulate an integer add unit, currently it will execute slower than a designed chip. It is the planning of the design and implementation of how you use the capabilities of the environment. It depends on the nature of the application and how you program. FPGA clock rates are slower than for microprocessors, but they can do a lot of parallel pipelining. Here is a very simple example. Instead of having one adder unit on a dedicated chip that is 2x as fast as the FPGA chip, you could program 100 on a chip to get a 50x speed up.

HPCwire: Will this first symposium lead to a permanent organization focused on FPGAs?

KW: That's another thing we'll discuss with the attendees. If there's enough interest, OSC will be happy to take the lead in continuing dialogue on FPGA technology. Yes, I think there SHOULD be a permanent one that focuses on FPGAs and HPC computing issues.