News Briefs - Hardware:

Chip Uses 100 Times Less Energy, Offers Exciting Potential

University of Alberta researchers have created a communications chip with exciting potential for unsurpassed energy efficiency.

The team at the iCORE High-Capacity Digital Communications Laboratory, in the Faculty of Engineering, have designed a computer chip that uses about 100 times less energy than current state-of-the-art digital chips.

The greatly reduced energy consumption of this novel technology offers promise for many small devices with relatively low power needs. This technology could one day eliminate the need to recharge cellphones, help introduce smaller, ultra-high-speed communications systems, and advance the use of implantable health care devices such a drug delivery chips. Research and development is ongoing before this technology can be implemented in products.

Professor Vincent Gaudet, iCORE Professor Christian Schlegel, and former graduate students Dave Nguyen and Chris Winstead collaborated on the project in the Department of Electrical and Computer Engineering. The communications chip was designed by Nguyen, manufactured by CMC (the Canadian Microelectronics Corporation) and tested at the University of Alberta.

This new analog processing technology has been used by Winstead to build the largest analog decoder chip fabricated to date, also built at iCORE's High- Capacity Digital Communications Laboratory at the University of Alberta. The iCORE HCDC Laboratory is a recognized world leader in this novel and promising technology.

"It is well known that there is a power barrier for future increases in process speeds and device sizes, and to overcome this, the world needs a new, disruptive technology," said Dr. Schlegel. "A fundamental new idea gave our team the edge, and we have been fortunate to have maintained a strong group here working on this technology for the last few years."

The invention employs a new method of processing digital data, known as analog decoding, which uses extremely low levels of power to execute its detection algorithm. The team's research shows no other reported chip uses a lower amount of energy consumed per decoded information bit.

The team has published two conference papers based on this project this year: one for the International Symposium on Turbo Codes in Brest, France, and another for the International Symposium on Circuits and Systems (ISCAS) in Vancouver.

The team has published two conference papers based on this project this year: one for the International Symposium on Turbo Codes in Brest, France (C. Winstead, D. Nguyen, V. Gaudet, and C. Schlegel, "Low-Voltage CMOS Translinear Circuits for Analog Decoders," Proceedings of the 3rd International Symposium on Turbo Codes and Related Topics, pages 271-274, Brest, France, September 2003) and another for the International Symposium on Circuits and Systems (ISCAS) in Vancouver (N. Nguyen, C. Winstead, V. Gaudet, and C. Schlegel, "A 0.8V CMOS Analog Decoder for an (8,4,4) Extended Hamming Code," IEEE International Symposium on Circuits and Systems, Vancouver, BC. Vol. I, pp. 1116-1119, May 2004.

The team's research is supported by iCORE, Science and Engineering Research Canada (more commonly known as NSERC), CMC (Canadian Microelectronics Corporation), the Canada Foundation for Innovation (CFI) and the Alberta Science and Research Authority (ASRA).